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24 Bit Stereo ADC
DESCRIPTION
The WM8738 is a high performance stereo audio ADC designed for consumer applications. Stereo line-level audio inputs are provided, along with a control input pin to allow operation of the audio interface in either one of two industry standard modes. The device also has a selectable digital high pass filter to remove residual DC offsets. Stereo 24-bit multi-bit sigma delta ADCs are provided, along with oversampling digital interpolation filters. 24-bit digital audio output word lengths and sampling rates from 32kHz to 96kHz are supported. The device is available in a small 14-lead SOIC package.
WM8738
FEATURES
* * * * * * * Audio Performance - 90 dB SNR (`A' weighted @ 48kHz) 3.0 - 5.5V Analogue Supply Operation 3.0 - 3.6V Digital Supply Operation ADC Sampling Frequency: 32kHz - 96kHz Selectable ADC High Pass Filter Selectable Audio Data Interface Modes - I2S or Left Justified 14-lead SOIC Package
APPLICATIONS
* * * CD and Minidisc Recorders DVD Players General Purpose Audio Conversion
BLOCK DIAGRAM
WOLFSON MICROELECTRONICS plc
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Production Data, August 2006, Rev 4.4
Copyright (c) 2006 Wolfson Microelectronics plc
WM8738 TABLE OF CONTENTS
Production Data
DESCRIPTION .......................................................................................................1 FEATURES.............................................................................................................1 APPLICATIONS .....................................................................................................1 BLOCK DIAGRAM .................................................................................................1 TABLE OF CONTENTS .........................................................................................2 PIN CONFIGURATION...........................................................................................3 ORDERING INFORMATION ..................................................................................3 PIN DESCRIPTION ................................................................................................4 ABSOLUTE MAXIMUM RATINGS.........................................................................5 RECOMMENDED OPERATING CONDITIONS .....................................................5 ELECTRICAL CHARACTERISTICS ......................................................................6 TERMINOLOGY .....................................................................................................7 DIGITAL AUDIO INTERFACE TIMING ..................................................................8 INTERNAL POWER ON RESET CIRCUIT ............................................................9 DEVICE DESCRIPTION.......................................................................................12
INTRODUCTION ......................................................................................................... 12 ADC............................................................................................................................. 12 ADC DIGITAL FILTER................................................................................................. 12 AUDIO DATA SAMPLING RATES............................................................................... 13 DIGITAL AUDIO INTERFACES................................................................................... 14
DIGITAL FILTER CHARACTERISTICS ...............................................................15 ADC FILTER RESPONSES .................................................................................15
ADC HIGH PASS FILTER ........................................................................................... 15
APPLICATIONS INFORMATION .........................................................................16
RECOMMENDED EXTERNAL COMPONENTS .......................................................... 16 RECOMMENDED EXTERNAL COMPONENTS VALUES ........................................... 16
PACKAGE DIMENSIONS ....................................................................................17 IMPORTANT NOTICE ..........................................................................................18
ADDRESS: .................................................................................................................. 18
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WM8738
Production Data
PIN CONFIGURATION
DVDD SDATO BCLK FMT CAP VREF RIN 1 2 3 4 5 6 7 WM8738 14 13 12 11 10 9 8 DGND MCLK LRCLK NOHP AGND AVDD LIN
ORDERING INFORMATION
DEVICE TEMPERATURE RANGE -25 to +85 C -25 to +85oC
o
PACKAGE 14-lead SOIC (Pb-free) 14-lead SOIC (Pb-free, tape and reel)
MOISTURE SENSITIVITY LEVEL
PEAK SOLDERING TEMPERATURE
WM8738GED/V
MSL2
260C
WM8738GED/RV Note: Reel quantity = 3,000
MSL2
260C
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WM8738 PIN DESCRIPTION
PIN 1 2 3 4 NAME DVDD SDATO BCLK FMT TYPE Supply Digital Output Digital Input Digital input (with pull down) Digital positive supply ADC digital data output ADC audio interface data clock (5V tolerant) Audio interface format selection (5V tolerant) `0' = I2S `1' = Left Justified Reference de-coupling pin Buffered reference decoupling pin Right channel ADC input Left channel ADC input Analogue positive supply Analogue ground supply and chip substrate Digital highpass filter bypass; (5V tolerant) `0' = Enabled `1' = Bypassed Data left/right word clock (5V tolerant) Master clock input (5V tolerant) Digital supply ground DESCRIPTION
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5 6 7 8 9 10 11
CAP VREF RIN LIN AVDD AGND NOHP
Analog Analogue output Analogue Input Analogue Input Supply Supply Digital input (with pull down)
12 13 14 Notes
LRCLK MCLK DGND
Digital Input Digital Input Supply
1. Digital input pins have Schmitt trigger input buffers and are 5V tolerant.
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WM8738 ABSOLUTE MAXIMUM RATINGS
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Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified. ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device. Wolfson tests its package types according to IPC/JEDEC J-STD-020B for Moisture Sensitivity to determine acceptable storage conditions prior to surface mount assembly. These levels are: MSL1 = unlimited floor life at <30C / 85% Relative Humidity. Not normally stored in moisture barrier bag. MSL2 = out of bag storage for 1 year at <30C / 60% Relative Humidity. Supplied in moisture barrier bag. MSL3 = out of bag storage for 168 hours at <30C / 60% Relative Humidity. Supplied in moisture barrier bag. CONDITION Digital supply voltage Analogue supply voltage Voltage range digital inputs Voltage range analogue inputs Master Clock Frequency Operating temperature range, TA Storage temperature prior to soldering Storage temperature after soldering Notes 1. 2. Analogue and digital grounds must always be within 0.3V of each other. The digital supply voltage must always be less than or equal to the analogue supply voltage. -25C MIN -0.3V -0.3V DGND -0.3V AGND -0.3V MAX +4.2V +7.0V +7.0V AVDD +0.3V 37MHz +85C
30C max / 85% RH max -65C +150C
RECOMMENDED OPERATING CONDITIONS
PARAMETER Digital supply range Analogue supply range Ground Analogue supply current Analogue supply current Supply Current Low Power Mode Supply Current Low Power Mode Digital supply current SYMBOL DVDD AVDD DGND,AGND AVDD = 5.0V, (DVDD at 3.3V) AVDD = 3.3V, (DVDD at 3.3V) AVDD = 5.0V (DVDD at 3.3V) AVDD = 3.3V (DVDD at 3.3V) DVDD = 3.3V AVDD = 5.0V or 3.3V TEST CONDITIONS MIN 3.0 3.0 0 30 19 TYP MAX 3.6 5.5 UNIT V V V mA mA A A mA
180 110 4
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WM8738 ELECTRICAL CHARACTERISTICS
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Test Conditions AVDD = 5.0V, AGND = 0V, DVDD = 3.3V, DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless otherwise stated. PARAMETER Digital Logic Levels (TTL Levels) Input LOW level Input HIGH level Output LOW Output HIGH Pull down resistance (FMT, NOHP) Analogue Reference Levels Reference voltage Buffered reference voltage Potential divider output impedance Input to ADC Input Signal Level (0dB) SNR (Note 1) SNR (Note 1) SNR (Note 1) VRIN / VLIN A-weighted, 0dB gain @ fs = 48KHz A-weighted, 0dB gain @ fs = 96KHz A-weighted, 0dB gain @ fs = 48KHz, AVDD = 3.3V DNR A-weighted, -60dB full scale input -1dB input, 0dB gain 1KHz input PSRR 1kHz 100mVp-p 20Hz to 20kHz 100mVp-p Input Resistance Input Capacitance Notes 1. 2. Ratio of output level with 1kHz full scale input, to the output level with the input open circuited, measured `A' weighted over a 20Hz to 20kHz bandwidth using an Audio analyser. All performance measurements done with 20kHz low pass filter, and where noted an A-weight filter. Failure to use such a filter will result in higher THD+N and lower SNR and Dynamic Range readings than are found in the Electrical Characteristics. The low pass filter removes out of band noise; although it is not audible it may affect dynamic specification values. VREF and CAP de-coupled with 10uF and 0.1uF capacitors (smaller values may result in reduced performance). This data is measured, using an active filter on the device inputs. 90 1.0 90 90 90 Vrms dB dB dB VCAP VREF RCAP 40 AVDD/2 - 50mV AVDD/2 VCAP 50 60 AVDD/2 + 50mV V V k VIL VIH VOL VOH RPD IOL = 1mA IOH = 1mA 0.9 x DVDD 100 2.0 0.1 x DVDD 0.8 V V V V k SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
Dynamic Range (Note 2) Total Harmonic Distortion (THD) (Note 3) ADC channel separation (Note 5) Power Supply Rejection Ratio
97 -87 95 50 45 20 10
dB dB dB dB dB k pF
3. 4.
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WM8738 TERMINOLOGY
1. 2.
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Signal-to-noise ratio (dB) - SNR is a measure of the difference in level between the full scale output and the output with no signal applied. (No `Auto-zero' or Automute function is employed in achieving these results). Dynamic range (dB) - DNR is a measure of the difference between the highest and lowest portions of a signal. Normally a THD+N measurement at 60dB below full scale. The measured signal is then corrected by adding the 60dB to it. (e.g. THD+N @ -60dB= -32dB, DR= 92dB). THD (dB) - THD is a ratio, of the r.m.s. values, of Distortion/Signal. Stop band attenuation (dB) - Is the degree to which the frequency spectrum is attenuated (outside audio band). Channel Separation (dB) - Also known as Cross-Talk. This is a measure of the amount one channel is isolated from the other. Normally measured by sending a full scale signal down one channel and measuring the other. Pass-Band Ripple - Any variation of the frequency response in the pass-band region.
3. 4. 5. 6.
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WM8738 DIGITAL AUDIO INTERFACE TIMING
tMCLKL M CLK tMCLKH tMCLKY
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Figure 1 Master Clock Timing Requirements
Test Conditions AVDD = 5.0V, AGND = 0V, DVDD = 3.3V, DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless otherwise stated. PARAMETER System Clock Timing Information
MCLK System clock pulse width high MCLK System clock pulse width low MCLK System clock cycle time
SYMBOL TMCLKH TMCLKL TMCLKY
TEST CONDITIONS
MIN 10 10 27
TYP
MAX
UNIT ns ns ns
t BCH BCLK t BCY
t BCL
LRCLK t DD SDATO t LRH t LRS U
Figure 2 Digital Audio Data Timing Test Conditions AVDD = 5.0V, AGND = 0V, DVDD = 3.3V, DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless otherwise stated. PARAMETER BCLK cycle time BCLK pulse width high BCLK pulse width low LRCLK set-up time to BCLK rising edge LRCLK hold time from BCLK rising edge SDATO propagation delay from BCLK falling edge SYMBOL tBCY tBCH tBCL tLRSU tLRH tDD TEST CONDITIONS MIN TYP 80 40 40 10 10 10 MAX UNIT ns ns ns ns ns ns Audio Data Input Timing Information
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WM8738 INTERNAL POWER ON RESET CIRCUIT
AVDD DVDD T1 100K CAP T2 VDD INTERNAL PORB
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Power On Reset Circuit
100K
Figure 2 Internal Power On Reset Circuit Schematic
The WM8738 includes an internal Power On Reset Circuit which is used reset the digital logic into a default state after power up. Figure 2 shows a schematic of the internal POR circuit. The circuit monitors DVDD and CAP and asserts PORB low if DVDD or CAP are below the minimum threshold Vpor_off. On power up, the POR circuit requires AVDD to be present to operate. PORB is asserted low until AVDD and DVDD and CAP are established. When AVDD, DVDD, and CAP have been established, PORB is released high, all registers are in their default state and writes to the digital interface may take place. On power down, PORB is asserted low whenever DVDD or CAP drop below the minimum threshold Vpor_off. In most applications the time required for the device to release PORB high will be determined by the charge time of the CAP node.
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WM8738
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Figure 3 Typical Power up sequence where DVDD is powered before AVDD
DVDD
DGND
AVDD
Vpora
Vpora_off
AGND
CAP Vporr AGND
HI INTERNAL PORB LO No Power POR Undefined Internal POR active Device Ready Internal POR active
Figure 4 Typical Power up sequence where AVDD is powered before DVDD
Typical POR Operation (typical values, not tested) SYMBOL Vpora Vporr Vpora_off Vpord_off MIN 0.5 0.5 1.0 0.6 TYP 0.7 0.7 1.4 0.8 MAX 1.0 1.1 2.0 1.0 UNIT V V V V
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WM8738
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In a real application the designer is unlikely to have control of the relative power up sequence of AVDD and DVDD. Using the POR circuit to monitor CAP ensures a reasonable delay between applying power to the device and Device Ready. Figure 3 and Figure 4 show typical power up scenarios in a real system. Both AVDD and DVDD must be established and CAP must have reached the threshold Vporr before the device is ready and can be written to. Any writes to the device before Device Ready will be ignored. Figure 3 shows DVDD powering up before AVDD. Figure 4 shows AVDD powering up before DVDD. In both cases, the time from applying power to Device Ready is dominated by the charge time of CAP. A 10uF cap is recommended for decoupling on CAP. The charge time for CAP will dominate the time required for the device to become ready after power is applied. The time required for VMIDADC to reach the threshold is a function of the CAP resistor string and the decoupling capacitor. The Resistor string has a typical equivalent resistance of 50k (+/-20%). Assuming a 10uF capacitor, the time required for CAP to reach threshold of 1V is approx 110ms.
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WM8738 DEVICE DESCRIPTION
INTRODUCTION
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The WM8738 is an ADC designed for audio recording. It's features, performance and low power consumption make it ideal for recordable CD or DVD players, karaoke, MP3 players and mini-disc players. The on-board stereo analogue to digital converter (ADC) is of a high quality using a multi-bit highorder oversampling architecture delivering optimum performance with low power consumption. The ADC includes a selectable digital high pass filter to remove unwanted DC components from the audio signal. The device supports system clock inputs of 256, 384, 512fs or 768fs (fs is the sampling rate) The output from the ADC is available on the digital audio interface in either I2S or left justified audio data formats. The line inputs are biased internally through the operational amplifier to VCAP.
ADC
The WM8738 uses a multi-bit over sampled sigma-delta ADC. A single channel of the ADC is illustrated in Figure 3.
LIN/RIN
ANALOG INTEGRATOR
TO ADC DIGITAL FILTERS
MULTI BITS
Figure 3 Multi-Bit Oversampling Sigma Delta ADC Schematic The use of multi-bit feedback and high oversampling rates reduces the effects of jitter and high frequency noise. The ADC Full Scale input is 1.0V rms at AVDD = 5.0 volts. Any voltage greater than full scale will possibly overload the ADC and cause distortion. Note that the full scale input tracks directly with AVDD. The ADC filters perform true 24 bit signal processing to convert the raw multi-bit oversampled data from the ADC to the correct sampling frequency to be output on the digital audio interface.
ADC DIGITAL FILTER
The ADC digital filters contain a digital high pass filter, selectable via pin NOHP. NOHP = 0 NOHP = 1 Digital high pass filter enabled Digital high pass filter bypassed
The high-pass filter response detailed in Digital Filter Characteristics. The operation of the high pass filter removes residual DC offsets that are present on the audio signal.
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WM8738
AUDIO DATA SAMPLING RATES
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In a typical digital audio system there is only one central clock source producing a reference clock to which all audio data processing is synchronised. This clock is often referred to as the audio system's Master Clock. The external master system clock can be applied directly through the MCLK input pin. In a system where there are a number of possible sources for the reference clock it is recommended that the clock source with the lowest jitter be used to optimise the performance of the ADC. The master clock for WM8738 supports audio sampling rates from 256fs to 768fs, where fs is the audio sampling frequency LRCLK, typically 32kHz, 44.1kHz, 48kHz, or 96kHz. The master clock is used to operate the digital filters and the noise shaping circuits. The WM8738 has a master clock detection circuit that automatically determines the relationship between the master clock frequency and the sampling rate (to within +/- 32 system clocks). If there is a greater than 32 clocks error the interface is disabled and maintains the output level at the last sample. The master clock must be synchronised with LRCLK, although the WM8738 is tolerant of phase variations or jitter on this clock. Table 1 shows the typical master clock frequency inputs for the WM8738. If MCLK is stopped for greater than 10us then the device will enter a low power mode where the current taken from AVDD is greatly reduced. Note that when the device enters this mode the references are powered down. Table 1 shows the common MCLK frequencies for different sample rates. SAMPLING RATE (LRCLK) 32kHz 44.1kHz 48kHz 96kHz Master Clock Frequency (MHz) 256fs 8.192 11.2896 12.288 24.576 384fs 12.288 16.9340 18.432 36.864 512fs 16.384 22.5792 24.576 768fs 24.576 33.8688 36.864
Unavailable Unavailable
Table 1 Master Clock Frequency Selection
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WM8738
DIGITAL AUDIO INTERFACES
The WM8738 has two data output formats, selectable via the FMT pin. FMT = 0 ADC audio data output is I2S FMT = 1 ADC audio data output is Left Justified Both of these modes are MSB first.
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The digital audio interface takes the data from the internal ADC digital filter. SDATO is the formatted digital audio data stream output from the ADC digital filters with left and right channels multiplexed together. LRCLK is an alignment clock that controls whether Left or Right channel data is present on the SDATO line. SDATO and LRCLK are synchronous with the BCLK signal with each data bit transition signified by a low to high BCLK transition.
LEFT JUSTIFIED MODE
In left justified mode, the MSB of the ADC data is output on SDATO and changes on the same falling edge of BCLK as LRCLK and may be sampled on the rising edge of BCLK. LRCLK is high during the left samples and low during the right samples.
1/fs
L EF T C H AN N EL LRCLK
R IGH T C H AN N EL
BCLK
SD ATO
1
2
3
n-2 n-1
n
1
2
3
n-2 n-1
n
M SB
LSB
M SB
LSB
Figure 4 Left Justified Mode Timing Diagram
I S MODE
In I2S mode, the MSB of the ADC data is output on SDATO and changes on the first falling edge of BCLK following an LRCLK transition and may be sampled on the rising edge of BCLK. LRCLK is low during the left samples and high during the right samples.
2
1/fs
LEFT C H AN N EL LR C LK
R IGH T C H AN N EL
B C LK
1 BCLK
1 BCLK 3 n-2 n-1 n 1 2 3 n-2 n-1 n
SD ATO
1
2
M SB
LSB
M SB
LSB
Figure 5 I2S Mode Timing Diagram
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WM8738 DIGITAL FILTER CHARACTERISTICS
PARAMETER Passband Stopband Passband ripple Stopband Stopband Attenuation Group Delay Table 2 Digital Filter Characteristics f > 0.5465fs 0.5465fs -65 22 SYMBOL TEST CONDITIONS 0.01 dB -6dB MIN 0 0.5fs 0.01 TYP MAX 0.4535fs
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UNIT dB dB dB Samples
ADC FILTER RESPONSES
0.02
0
0.015 0.01
-20
Response (dB)
Response (dB)
0.005 0 -0.005 -0.01 -0.015 -0.02
-40
-60
-80
0
0.5
1
1.5 Frequency (Fs)
2
2.5
3
0
0.05
0.1
0.15
0.2 0.25 0.3 Frequency (Fs)
0.35
0.4
0.45
0.5
Figure 6 ADC Digital Filter Frequency Response
Figure 7 ADC Digital Filter Ripple
ADC HIGH PASS FILTER
The WM8738 has a selectable digital highpass filter to remove DC offsets. The filter response is characterised by the following polynomial.
H(z) =
1 - z-1 1 - 0.9995z-1
0
Response (dB)
-5
-10
-15
0
0.0005
0.001 Frequency (Fs)
0.0015
0.002
Figure 8 ADC Highpass Filter Response
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WM8738 APPLICATIONS INFORMATION
RECOMMENDED EXTERNAL COMPONENTS
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DVDD 1 + C1 C2 14 DGND DVDD AVDD AGND 9 C3 10 C4
AVDD +
AGND
DVDD 4 R FMT
LIN
8
C5 R C6
1
Hardware Control
2
WM8738
DVDD 11 R
3
NOHP
RIN
7
C
7
R C
8
4
13
Audio Serial Data I/F
3 12 2
MCLK BCLK LRCLK SDATO
VREF
6 C9 C10 +
CAP
5 C 11
AGND C 12 +
AGND
Notes: 1. AGND and DGND should be connected as close to the WM8738 as possible. 2. C2, C3, C9 and C11 should be positioned as close to the WM8738 as possible. 3. Capacitor types should be carefully chosen. Capacitors with very low ESR are recommended for optimum performance.
Figure 9 External Components Diagram
RECOMMENDED EXTERNAL COMPONENTS VALUES
COMPONENT REFERENCE C1 and C4 C2 and C3 C5 and C7 C6 and C8 R2 and R3 R1 and R4 C9 C10 C11 C12 SUGGESTED VALUE 10F 0.1F 1F 4.7nF 10k 680 0.1F 10F 0.1F 10F Reference de-coupling capacitors for CAP pin DESCRIPTION De-coupling for DVDD and AVDD De-coupling for DVDD and AVDD Analogue input AC coupling caps Analogue input filtering (RC) capacitor Current limiting resistors Analogue input filtering (RC) resistor Reference de-coupling capacitors for VREF pin
Table 3 External Components Description
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WM8738 PACKAGE DIMENSIONS
D: 14 PIN SOIC 3.9mm Wide Body
Production Data
DM001.C
e
B
14
8
H E
1
7
D
L h x 45o
A1 -CA
SEATING PLANE
C
0.10 (0.004)
Symbols A A1 B C D E e H h L REF:
Dimensions (mm) MIN MAX 1.35 1.75 0.10 0.25 0.33 0.51 0.19 0.25 8.55 8.75 3.80 4.00 1.27 BSC 5.80 6.20 0.25 0.50 0.40 1.27 o o 0 8 JEDEC.95, MS-012
Dimensions (Inches) MIN MAX 0.0532 0.0688 0.0040 0.0098 0.0130 0.0200 0.0075 0.0098 0.3367 0.3444 0.1497 0.1574 0.05 BSC 0.2284 0.2440 0.0099 0.0196 0.0160 0.0500 o o 0 8
NOTES: A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS (INCHES). B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE. C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.25MM (0.010IN). D. MEETS JEDEC.95 MS-012, VARIATION = AB. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS.
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WM8738 IMPORTANT NOTICE
Production Data
Wolfson Microelectronics plc ("Wolfson") products and services are sold subject to Wolfson's terms and conditions of sale, delivery and payment supplied at the time of order acknowledgement.
Wolfson warrants performance of its products to the specifications in effect at the date of shipment. Wolfson reserves the right to make changes to its products and specifications or to discontinue any product or service without notice. Customers should therefore obtain the latest version of relevant information from Wolfson to verify that the information is current.
Testing and other quality control techniques are utilised to the extent Wolfson deems necessary to support its warranty. Specific testing of all parameters of each device is not necessarily performed unless required by law or regulation.
In order to minimise risks associated with customer applications, the customer must use adequate design and operating safeguards to minimise inherent or procedural hazards. Wolfson is not liable for applications assistance or customer product design. The customer is solely responsible for its selection and use of Wolfson products. Wolfson is not liable for such selection or use nor for use of any circuitry other than circuitry entirely embodied in a Wolfson product.
Wolfson's products are not intended for use in life support systems, appliances, nuclear systems or systems where malfunction can reasonably be expected to result in personal injury, death or severe property or environmental damage. Any use of products by the customer for such purposes is at the customer's own risk.
Wolfson does not grant any licence (express or implied) under any patent right, copyright, mask work right or other intellectual property right of Wolfson covering or relating to any combination, machine, or process in which its products or services might be or are used. Any provision or publication of any third party's products or services does not constitute Wolfson's approval, licence, warranty or endorsement thereof. Any third party trade marks contained in this document belong to the respective third party owner.
Reproduction of information from Wolfson datasheets is permissible only if reproduction is without alteration and is accompanied by all associated copyright, proprietary and other notices (including this notice) and conditions. Wolfson is not liable for any unauthorised alteration of such information or for any reliance placed thereon.
Any representations made, warranties given, and/or liabilities accepted by any person which differ from those contained in this datasheet or in Wolfson's standard terms and conditions of sale, delivery and payment are made, given and/or accepted at that person's own risk. Wolfson is not liable for any such representations, warranties or liabilities or for any reliance placed thereon by any person.
ADDRESS:
Wolfson Microelectronics plc Westfield House 26 Westfield Road Edinburgh EH11 2QB United Kingdom Tel :: +44 (0)131 272 7000 Fax :: +44 (0)131 272 7001 Email :: sales@wolfsonmicro.com
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